Applications:
(CPO) / Co-Packaged Optics (CPO)
Perfectly suited for CPO architectures where optical engines are integrated alongside high-bandwidth ASICs. The dual-layer design provides the necessary port density required to handle massive data throughput in tight packaging spaces.
Silicon Photonics (SiPh) Edge Coupling
As silicon photonic chips incorporate more waveguides per millimeter, dual-layer FAUs allow coupling to densely packed 2D waveguide arrays or grating couplers without increasing the chip edge length.
Ultra-High Density Optical Interconnects & Testing
Used in high-density parallel optical transceivers (800G/1.6T+), optical backplanes, and multi-channel automated test equipment (ATE) where maximizing channel count per probe is critical.
Compliance & Quality:
Manufactured under ISO 9001:2015 quality management systems and fully RoHS compliant. Each dual-layer array undergoes rigorous 3D dimensional inspection to verify layer alignment, and 100% optical testing (IL/RL) across all channels to guarantee premium performance and reliability.
For custom 2D layouts, specific layer pitches, or volume quotations, please contact our sales engineering team.
